The present disclosure relates to an electro-optical detectors and, more particularly, for a latch to hold command words for such electro-optical detectors.
Over the last few years, electro-optical sensors have been developed that incorporate increasingly higher resolution. Such detectors may have different operations modes or settings that need to be stored or altered.
In particular, such sensors may include a read-out integrated circuit (ROIC) that reads out the information received by an array of pixels. In certain cases, the ROIC may have different operations settings that need to be maintained.
Many ROIC's may be used for infrared imaging and require cooling to cryogenic temperatures to improve image quality. Power dissipation on ROIC is extremely critical for these applications since current coolers have low efficiency and the entire assembly may be mobile (e.g. vehicle, airborne or space craft) where system power is limited.
Traditionally, the ROIC's has been designed to receive the entire external commanding dataword (e.g., setting) periodically to refresh all dataword control bits on-chip. As ROIC's become more and more complex, this commanding dataword keeps increasing in size an can lead to increased excessive power dissipation from internal dataword management and distribution as well as increased complexity in the controlling system, having to store and transmit the dataword continuously. From time to time herein, the commanding dataword may be referred to as a command or control word.
In some cases, external events (such as a single event upset (SEU)) can cause the one or more bits of the dataword to be altered. An example of such an SEU is the effect of a lower power radiation event being experience by a satellite. If the SEU causes one of the bits of the control dataword to change, the operational mode of the ROIC may change in a manner that is not desired by the operator.
One approach to protect the datawords is to continuously refresh the dataword storage in the ROIC from an external controller. As the ROIC complexity increases and the number of control bits increases, the additional power and system complexity in having to re-transmit all datawords periodically becomes critical. Another approach to protect the datawords is to provide redundancy of each the dataword. Prior attempts at TMR (Triple Modular Redundancy) involved a “scrubbing” circuit that would periodically (e.g. every 30 ms) check the status of the three storage sites, vote amongst the three sites and write back the voted result to all three sites. This approach, while effective, may draw more power than is desired as all register bits have to be read, voted and written back at a high repetition rate. Further, such a solution may require additional complexity and power dissipation in on-chip timing controllers that have to cycle/vote each bit. Another concern is that if two SEU events toggles two of the three sites at different times, but before the scrubbing circuit had a chance to visit the cell for correction of the first SEU event, the digital bit would be permanently flipped.